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STRUCTURE NAME OF PRODUCT TYPE FUNCTION
Silicon Monolithic Integrated Circuit DC-AC Inverter Control IC
,
36V High voltage process 1ch control with Half-bridge Lamp current and voltage sense feed back control Sequencing easily achieved with Soft Start Control Short circuit protection with Timer Latch Under Voltage Lock Out Mode-selectable the operating or stand-by mode by stand-by pin
Absolute Maximum RatingsTa = 25
Parameter Supply Voltage
BST BST-ST Voltage Difference
Operating Temperature Range Storage Temperature Range Power Dissipation Maximum Junction Temperature
*1 *2
Symbol VCC BST BST-SW Topr Tstg Pd Tjmax
Limits 30 40 15 -40+85 -55+150 550*1(BD9883AF) 650*2(BD9883FV) +150
Unit V V V mW
Pd derated at 4.4mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm)
Pd derated at 5.2mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm)
Recommended operating condition
Parameter Supply voltage CT oscillation frequency
BST voltage BST-SW voltage difference
Symbol Vcc fCT BST BST-SW fBCT
Limits 6.022.0 20150 4.034.0 4.012.0 0.100.50
Unit V kHz V V kHz
BCT oscillation frequency
REV. E
2/4 Electric CharacteristicsTa=25VCC=12V
Limits Parameter WHOLE DEVICE Operating current Stand-by current STAND BY CONTROL Stand-by voltage H Stand-by voltage L Stand-by hysteresis UVLO BLOCK Operating voltage Shut down voltage REG BLOCK REG output voltage REG source current OSC BLOCK Active edge current Negative edge current OSC Max voltage OSC Min voltage OSC Min voltage Soft start current SRT ON resistance BOSC BLOCK BOSC Max voltage BOSC Min Voltage BOSC constant current TIMER LATCH Timer Latch voltage Timer Latch current FEED BACK BLOCK IS threshold voltage VS threshold voltage IS source current 1 IS source current 2 VS source current FB over voltage detect voltage IS COMP detect Voltage OUTPUT BLOCK LN output sink current LN output source current HN output sink current HN output source current RsinkLN RsourceLN RsinkHN RsourceHN 15 30 15 30 30 60 30 60 VBST-VSW=5.0V VBST-VSW=5.0V Vis Vvs Iis1 Iis2 Ivs Vovf Visc 1.220 1.220 12.0 2.2 0.3 1.250 1.250 20.0 2.5 0.4 1.280 1.280 0.9 28.0 0.9 2.8 0.5 V V A A A V V DUTY=2.0V DUTY=0VIS=0.5V Vscp Iscp 1.8 0.25 2.0 0.50 2.2 0.75 V A VBCTH VBCTL IBCT 1.920 0.400 1.35/BRT 2.000 0.500 1.5/BRT 2.080 0.600 1.65/BRT V V A fBCT=0.3kHz fBCT=0.3kHz VBCT=0.2V Iact Ineg VoscH VoscL1 VoscL2 Iss RSRT 1.35/RT Iactx10 1.8 0.2 0.05 0.50 1.5/RT Iactx13 2.0 0.4 0.15 1.00 150 1.65/RT Iactx16 2.2 0.6 0.25 1.50 300 A A V V V A fCT=50kHz, fCT=120kHz fCT=50kHz fCT=120kHz VREG IREG 5.30 20.0 5.50 5.70 V mA Vcc6.0V VuvloH VuvloL 5.15 4.90 5.40 5.15 5.65 5.40 V V VstH VstL Vst 1.7 -0.3 0.05 0.20 VCC 0.7 0.35 V V V System System Icc1 Icc2 9.0 5.0 17.0 10.0 mA A fCT=100kHz Symbol MIN. TYP. MAX. Unit Conditions
This product is not designed for normal operation with in a radio active environment.
REV. E
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Package Dimensions
(Include BURR 12.85)
Device Mark
Device Mark
BD9883AF
BD9883
Lot No.
Lot No.
SOP20 (Unit:mm)
SSOP-B20 (Unit:mm)
Block Diagram
SS CT RT BRT BCT DUTY VCC
Pin Description
Pin No. 1 2
VCC PWM BLOCK REG BLOCK LOGIC BLOCK VCC HN OUTPUT BLOCK LN OUTPUT BLOCK REG BST HN SW LN PGND
Pin Name DUTY BCT BRT CT RT SRT GND FB IS VS STB SCP SS PGND LN HN SW BST REG VCC
Function Control PWM mode and BURST mode External capacitor from BCT to GND for adjusting the BURST triangle oscillator External resistor from BRT to GND for adjusting the BURST triangle oscillator External capacitor from CT to GND for adjusting the triangle oscillator External resistor from RT to GND for adjusting the triangle oscillator External resistor from SRT to RT for adjusting the triangle oscillator GROUND Error amplifier output Error amplifier input Error amplifier input Stand-by switch External capacitor from SCP to GND for Timer Latch External capacitor from SS to GND for Soft Start Control Ground for FET drivers NMOS FET driver NMOS FET driver Low voltage for HN output Boot-Strap input for HN output Internal regulator output Supply voltage input
+
OSC STB STB BLOCK BOSC
-
SYSTEM ON/OFF
3 4 5 6 7 8 9 10
FB
IS
+
F/B BLOCK
VS
+
+
UVLO
VS IS PROTECT BLOCK
11 12 13
GND
SCP
SRT
14 15 16 17 18 19 20
REV. E
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NOTE FOR USE
When designing the external circuit, including adequate margins for variation between external devices and the IC.Use adequate margins for steady state and transient characteristics. Recommended Operating Range The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however, the variation will be small. Mounting Failures Mounting failures, such as misdirection or miscounts, may harm the device. Electromagnetic Fields A strong electromagnetic field may cause the IC to malfunction. . The GND pin should be the location within 0.3V compared with the PGND pin
BD9883AF, BD9883FV has the short circuit protection with Thermal Shut Down System. When STB or Vcc pin re-supplied, They enables to cancel the latch. If It rise the temperature of the chip more than 170(TYP), It make the external FET OFF Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch. By STB voltage, BD9883AF,BD9883FV is changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.71.7V). The pin connected a connector need to connect to the resistor for electrical surge destruction. This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, (When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) (When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND(P substrate)voltage to an input pin.
(PinA) Resistance (PinB) Transistor (NPN) B E C
GND P P N P substrate GND Parasitic diode N P P substrate GND Parasitic diode (PinB) (PinA) B Parasitic diode GND Other adjacent components Parasitic diode
N
N
C E GND
-1 Simplified structure of a Bipolar IC
REV. E
Notice
Notes
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